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order number: 251407, revision: 010 18-oct-2005 intel ? wireless flash memory (w18/w30 scsp) 32wq and 64wq family with asynchronous ram datasheet product features the intel ? wireless flash memory (w18/w30 scsp) family offers various flash plus static ram combinations in a common package footprint. the flash memory features 1.8 v low- power operations with flexible, multi-partition, dual-operation read-while-write / read-while- erase, asynchronous, and synchronous reads. this scsp device integrates up to two flash die, one psram die, and one sram die in a low-profile package compatible with other scsp families with quad+ ballout. device architecture ? flash density: 32-mbit, 64-mbit ? async psram density: 8-, 16-, 32- mbit; async sram density: 4-, 8-, 16- mbit ? top, bottom or dual flash parameter configuration device voltage ?flash v cc = 1.8 v; flash v ccq = 1.8 v or 3.0 v ?ram v cc = 3.0 v; ram v ccq = 1.8 v or 3.0 v device packaging ? 88 balls (8 x 10 active ball matrix); area: 8x10 mm; height: 1.2 mm to 1.4 mm psram performance ? 70 ns initial access, 25 ns async page reads at 1.8 v i/o ? 70 ns initial access async psram at 1.8v i/o ? 88 ns initial access, 30 ns async page reads at 1.8 v i/o ? 85 ns initial access, 35 ns async page reads at 3.0 v i/o ? 70 ns initial access, 25 ns async page reads at 3.0 v i/o sram performance ? 70 ns initial access at 1.8 v or 3.0 v i/o flash performance ? 65 ns initial access at 1.8 v i/o ? 70 ns initial access at 3.0 v i/o ? 25 ns async page at 1.8 v or 3.0 v i/o ? 14 ns sync reads (t chqv ) at 1.8 v i/o ? 20 ns sync reads (t chqv ) at 3.0 v i/o ? enhanced factory programming: 3.10 s/word (typ) flash architecture ? read-while-write/erase ? asymmetrical blocking structure ? 4-kword parameter blocks (top or bottom); 32-kword main blocks ? 4-mbit partition size ? 128-bit one-time programmable (otp) protection register ? zero-latency block locking ? absolute write protection with block lock using f-vpp and f-wp# flash software ?intel ? flash data integrator (fdi) and common flash interface (cfi) quality and reliability ? extended temperature: ?25 c to +85 c ? minimum 100k flash block erase cycle ? 90 nm etox? ix flash technology ? 130 nm etox? viii flash technology
18-oct-2005 intel? wireless flash memory (w18/w30 scsp) datasheet 2 order number: 251407, revision: 010 le ga l lin es an d discla ime rs information in this document is provided in connection with intel? products. no license, express or implied, by estoppel or otherwise, to any intellectual property righ ts is granted by this document. except as provided in intel's terms and conditions of sale for such products, intel assu mes no liability whatsoever, and intel disclaims any express or implied warranty, relating to sale and/or use of intel product s including liability or warranties relating to fitness for a particular purpose, merchantability, or infringeme nt of any patent, copyright or other intellectual property right. intel products are not intended for use in medical, life saving, life sustaining, critical control or safety systems, or in nuclear facility applications. intel may make changes to specifications and product descriptions at any time, without notice. intel corporation may have patents or pending patent applications, trademarks, copyrights, or other intellectual property right s that relate to the presented subject matter. the furnishing of documents and other materials and information does not provide any license, express or implied, by estoppel or otherwise, to any such patents, trademarks, copyrights, or other intellectual property rights. contact your local intel sales office or your distributor to obtain the latest specifications and before placing your product o rder. copies of documents which have an order number and are referenced in this document, or other intel literature may be obtained b y calling 1-800-548-4725 or by visiting intel's website at http://www.intel.com . *other names and brands may be claimed as the property of others. copyright ? 2005, intel corporation. all rights reserved.
32wq and 64wq family?intel? wireless flash memory (w18/w30 scsp) datasheet intel? wireless flash memory (w18/w30 scsp) 18-oct-2005 order number: 251407, revision: 010 3 1.0 introduction ............................................................................................................................... .....6 1.1 nomenclature ................................................................................................................ ....... 6 1.2 conventions................................................................................................................. ......... 6 2.0 functional overview .....................................................................................................................8 2.1 block diagram ............................................................................................................... ....... 8 2.2 flash memory map and partitioning ..................................................................................... 9 3.0 package information ...................................................................................................................11 4.0 ballout and signal description ..................................................................................................13 4.1 signal ballout.............................................................................................................. ........13 4.2 signal descriptions ......................................................................................................... ....14 5.0 maximum ratings and operating conditions ...........................................................................16 5.1 absolute maximum ratings ................................................................................................ 16 5.2 operating conditions ........................................................................................................ .. 17 5.3 capacitance................................................................................................................. ....... 17 6.0 electrical specifications .............................................................................................................18 6.1 dc characteristics.......................................................................................................... .... 18 7.0 ac characteristics ......................................................................................................................21 7.1 flash ac characteristics .................................................................................................... 21 7.2 sram ac characteristics...................................................................................................21 7.3 psram ac characteristics ................................................................................................ 24 7.4 device ac test conditions................................................................................................. 29 8.0 flash power consumption .........................................................................................................30 9.0 device operation ......................................................................................................................... 31 9.1 bus operations .............................................................................................................. .....31 9.2 flash command definitions................................................................................................ 34 10.0 flash read operations ............................................................................................................... 35 11.0 flash program operations .........................................................................................................36 12.0 flash erase operations .............................................................................................................. 37 13.0 flash security modes .................................................................................................................. 38 14.0 flash read configuration register ........................................................................................... 39 15.0 sram operations ........................................................................................................................ 40 15.1 power-up sequence and initialization ................................................................................ 40 15.2 data retention mode........................................................................................................ .. 40 16.0 psram operations ......................................................................................................................42 16.1 power-up sequence and initialization................................................................................ 42 16.1.1 16mbit psram power-up sequence (non-page mode).......................................42 16.2 standby mode/ deep power-down mode .......................................................................... 43 16.3 psram special read and write constraints .....................................................................43
intel? wireless flash memory (w18/w30 scsp)?32wq and 64wq family 18-oct-2005 intel? wireless flash memory (w18/w30 scsp) datasheet 4 order number: 251407, revision: 010 appendix a write state machine ........................................................................................................ 45 appendix b common flash interface ................................................................................................. 46 appendix c flash flowcharts .............................................................................................................47 appendix d additional information .................................................................................................... 48 appendix e ordering information ....................................................................................................... 49
32wq and 64wq family?intel? wireless flash memory (w18/w30 scsp) datasheet intel? wireless flash memory (w18/w30 scsp) 18-oct-2005 order number: 251407, revision: 010 5 revision history date revision description june 2003 -001 initial release. september 2003 -002 changed psram read values. added new transient equivalent testing load circuit figure. general text edits. may 2004 -006 reformatted the datasheet and moved sections around according to the new layout. august 2004 -007 added 90 nm product information. added line items to table 21 ?32wq and 64wq w18/w30 scsp ordering information (flash only)? on page 50 . added dc and ac specs for the new line items and edits to related sections. january 2005 -008 added line items to table 21 ?32wq and 64wq w18/w30 scsp ordering information (flash only)? on page 50 added 32wq product information. june 2005 -009 added line items to table 21 ?32wq and 64wq w18/w30 scsp ordering information (flash only)? on page 50 october 2005 -010 removed power-up sequence from section 16; added 70ns psram (non-page mode) specification updated ordering information
intel? wireless flash memory (w18/w30 scsp) 18-oct-2005 intel? wireless flash memory (w18/w30 scsp) datasheet 6 order number: 251407, revision: 010 1.0 introduction this document contains information pertaining to the products in the intel ? wireless flash memory (w18/w30 scsp) family with asynchronous ram. the w18/w30 scsp 32wq and 64wq families offer a wide variety of stacked combinations that include single flash die, two flash die, flash + psram, and flash + sram options.this document provides information where this scsp family differs from the intel ? wireless flash memory (w18/w30) discrete device. refer to the discrete datasheets intel? wireless flash memory (w18) datasheet (order number 290701) and intel ? wireless flash memory (w30) datasheet (order number 290702) for flash product details not included in this scsp datasheet. 1.1 nomenclature 0x hexadecimal prefix 0b binary prefix byte 8 bits cfi common flash interface cui command user interface du don?t use etox eprom tunnel oxide fdi flash data integrator (intel ? software solution) k (noun) 1 thousand kb 1024 bits kb 1024 bytes kword 1024 words m (noun) 1 million mb 1,048,576 bits mb 1,048,576 bytes otp one-time programmable plr protection lock register pr protection register prd protection register data rcr read configuration register rfu reserved for future use scsp stacked chip scale package sr status register srd status register data word 16 bits wsm write state machine 1.2 conventions group membership brackets: square brackets are used to designate group membership or to define a group of signals with a similar function, such as a[21:1] and sr[4,1]. vcc vs. v cc : when referring to a signal or package-connection name, the notation used is vcc, etc. when referring to a timing or electrical level, the notation used is subscripted such as v cc , etc.
intel? wireless flash memory (w18/w30 scsp) datasheet intel? wireless flash memory (w18/w30 scsp) 18-oct-2005 order number: 251407, revision: 010 7 device: this term is used interchangeably throughout this document to denote either a particular die, or the combination of multiple die within a single package. f[3:1]-ce#, f[2:1]-oe#: this is the method used to refer to more than one chip-enable or output enable at the same time. when each is referred to individually, the reference will be f1- ce# and f1-oe# (for die #1), and f2-ce# and f2-oe# (for die #2). f-vcc, p-vcc or s-vcc: when referencing flash memory signals or timings, the notation used is f-vcc or f-v cc, respectively. when the reference is to psram signals or timings, the notation is prefixed with ?p-? (e.g., p-vcc, p-v cc ). when referencing sram signals or timings, the notation is prefixed with ?s-? (e.g., s-vcc or s-v cc ). p-vcc and s-vcc are rfu for stacked combinations that do not include psram or sram. r-oe#, r-lb#, r-ub#, r-we#: these are used to identify ram oe#, lb#, ub#, we# signals, and are usually shared between 2 or more ram die. r-oe#, r-lb#, r-ub# and r-we are rfu for stacked combinations that do not include psram or sram.
intel? wireless flash memory (w18/w30 scsp) 18-oct-2005 intel? wireless flash memory (w18/w30 scsp) datasheet 8 order number: 251407, revision: 010 2.0 functional overview this section provides an overview of the features and capabilities of the intel? wireless flash memory (w18/w30 scsp) family with asynchronous ram device. the w18/w30 scsp device provides flash + ram die combinations. products range from single flash die, two flash die, flash + psram, or flash + sram. you can choose a w18 scsp device or a w30 scsp device with sram or psram offered with the same package footprint and signal ballout. table 21 on page 50 lists possible product combinations for the 32-mbit and 64-mbit w18/w30 scsp family. 2.1 block diagram figure 1 shows all internal package connections for the scsp family with multiple die. see table 21 for valid combinations of flash and ram die. unused connections on combinations with less than three die are reserved and should not be used. please contact your local intel representative for details regarding any reserved or rfu pins. figure 1. block diagram flash die #2 32- or 64-mbit w18/w30 ram die 4-, 8-, 16-mbit sram or 16- or 32-mbit psram flash die #1 32- or 64-mbit w18/w30 f2-vcc s-vcc/p-vcc f2-ce# f2-oe# r-we# r-ub# r-lb# s-cs2 vss f1-vcc f1-ce# f1-oe# a[max:0] p-cs#/s-cs1# r-oe# a[max:0] d[15:0] clk f-wp# adv# f-rst# f-we# vccq f-vpp wait p-mode
intel? wireless flash memory (w18/w30 scsp) datasheet intel? wireless flash memory (w18/w30 scsp) 18-oct-2005 order number: 251407, revision: 010 9 2.2 flash memory map and partitioning consult the latest intel ? wireless flash memory (w18) datasheet (order number 290701) and the intel ? wireless flash memory (w30) datasheet (order number 290702), for individual flash die memory map and partitioning information. table 1 and table 2 show memory map and partitioning information for dual-flash memory die configurations. flash die #1 (with f1-ce# as its chip select) is configured as a bottom boot while flash die #2 (with f2-ce# as its chip select) is configured as top boot. table 1. 64-mbit flash + 32-mbit flash die w18/w30 scsp memory map and partitioning partitioning block size (kw) block # address range flash die #2 (32-mbit) parameter partition partition 0 4 63-70 1f8000-1fffff 32 56-62 1c0000-1f7fff main partitions partition 1 32 48-55 180000-1bffff partition 2 32 40-47 140000-17ffff partition 3 32 32-39 100000-13ffff partitions 4-7 32 0-31 000000-0fffff flash die #1 (64-mbit) main partitions partitions 8-15 32 71-134 200000-3fffff partitions 4-7 32 39-70 100000-1fffff partition 3 32 31-38 0c0000-0fffff partition 2 32 23-30 080000-0bffff partition 1 32 15-22 040000-07ffff parameter partition partition 0 32 8-14 008000-03ffff 4 0-7 000000-007fff
intel? wireless flash memory (w18/w30 scsp) 18-oct-2005 intel? wireless flash memory (w18/w30 scsp) datasheet 10 order number: 251407, revision: 010 table 2. 64-mbit dual-flash die w18/w30 scsp memory map and partitioning partitioning block size (kw) block # address range top parameter parameter partition partition 0 4 127-134 3f8000-3fffff 32 120-126 3c0000-3f7fff main partitions partition 1 32 112-119 380000-3bffff partition 2 32 104-111 340000-37ffff partition 3 32 96-103 300000-33ffff partitions 4-7 32 64-95 200000-2fffff partitions 8-15 32 0-63 000000-1fffff bottom parameter main partitions partitions 8-15 32 71-134 200000-3fffff partitions 4-7 32 39-70 100000-1fffff partition 3 32 31-38 0c0000-0fffff partition 2 32 23-30 080000-0bffff partition 1 32 15-22 040000-07ffff parameter partition partition 0 32 8-14 008000-03ffff 4 0-7 000000-007fff
intel? wireless flash memory (w18/w30 scsp) datasheet intel? wireless flash memory (w18/w30 scsp) 18-oct-2005 order number: 251407, revision: 010 11 3.0 package information the following packages are offered with the 32wq and 64wq family: ? figure 2, ?mechanical specifications for 1- or 2-die scsp device (8x10x1.2 mm)? ? figure 3, ?mechanical specifications for triple-die scsp device (8x10x1.4 mm)? figure 2. mechanical specifications for 1- or 2-die scsp device (8x10x1.2 mm) millimeters inches di me ns i ons s ymbol mi n nom max note s mi n nom m a package height a 1.200 0.04 ball height a1 0.200 0.0079 packag e bod y th ickn es s a2 0.860 0.0339 ball (lead) width b 0.325 0.375 0.425 0.0128 0.0148 0.01 package body length d 9.900 10.000 10.100 0.3898 0.3937 0.39 package body width e 7.900 8.000 8.100 0.3110 0.3150 0.31 pitch e 0.800 0.0315 ball (lead) count n 88 88 seating plane coplanarity y 0.100 0.00 corner to ball a1 distance along e s1 1.100 1.200 1.300 0.0433 0.0472 0.05 corner to ball a1 distance along d s2 0.500 0.600 0.700 0.0197 0.0236 0.02 top view - ball down bottom view - ball up a a2 d e y a1 drawing not to scale. s2 a c b e d g f j h k l m e 1 2 3 4 5 6 7 8 b a c b e d g f j h k l m m ar k 123 456 78
intel? wireless flash memory (w18/w30 scsp) 18-oct-2005 intel? wireless flash memory (w18/w30 scsp) datasheet 12 order number: 251407, revision: 010 figure 3. mechanical specifications for triple-die scsp device (8x10x1.4 mm) millimeters inches dimens ions symbol min nom max notes min nom max package height a 1.400 0.0551 ball height a1 0.200 0.0079 package body thickness a2 1.070 0. 0421 ball (lead) width b 0.325 0.375 0.425 0.0128 0.0148 0.0167 package body length d 9.900 10.000 10.100 0. 3898 0.3937 0.3976 package body width e 7.900 8.000 8.100 0. 3110 0.3150 0.3189 pitch e 0.800 0.0315 ball (lead) count n 88 88 seating plane coplanarity y 0.100 0.0039 corner to ball a1 distance along e s1 1.100 1.200 1.300 0. 0433 0.0472 0.0512 corner to ball a1 distance along d s2 0.500 0.600 0.700 0. 0197 0.0236 0.0276 top view - ball down bottom view - ball up a a2 d e y a1 drawing not to scale. s2 s1 a c b e d g f j h k l m e 1 2 3 4 5 6 7 8 b a c b e d g f j h k l m a1 index mark 1 234 567 8
intel? wireless flash memory (w18/w30 scsp) datasheet intel? wireless flash memory (w18/w30 scsp) 18-oct-2005 order number: 251407, revision: 010 13 4.0 ballout and signal description 4.1 signal ballout figure 4 shows the 32wq and 64wq w18/w30 scsp family 88-ball (8x10 active ball matrix) device. figure 4. 88-ball (8x10 active ball matrix) quad+ ballout 12345678 a du du du du a b a4 a18 a19 vss f1-vcc f2-vcc a21 a11 b c a5 r-lb# a23 vss s-cs2 clk a22 a12 c d a3 a17 a24 f-vpp r-we# p1-cs# a9 a13 d e a2 a7 a25 f-wp# adv# a20 a10 a15 e f a1 a6 r-ub# f-rst# f-we# a8 a14 a16 f g a0 dq8 dq2 dq10 dq5 dq13 wait f2-ce# g h r-oe# dq0 dq1 dq3 dq12 dq14 dq7 f2-oe# h j s-cs1# f1-oe# dq9 dq11 dq4 dq6 dq15 vccq j k f1-ce# p2-cs# f3-ce# s-vcc p-vcc f2-vcc vccq p-mode/ p-cre k l vss vss vccq f1-vcc vss vss vss vss l m du du du du m 12345678 top view - ball side down sram/psram specific de-populated balls global signals legend: do not use flash specific
intel? wireless flash memory (w18/w30 scsp) 18-oct-2005 intel? wireless flash memory (w18/w30 scsp) datasheet 14 order number: 251407, revision: 010 4.2 signal descriptions table 3 describes active signals used on the 32wq and 64wq w18/w30 scsp family. table 3. signal descriptions (sheet 1 of 2) symbol type name and function a[21:0] input address inputs: inputs for all die addresses during read and write operations. addresses are internally latched during write operations. ? 4-mbit: a[17:0] ? 8-mbit: a[18:0] ? 16-mbit: a[19:0] ? 32-mbit: a[20:0] ? 64-mbit: a[21:0] a0 is the lowest-order word address. a[25:22] denote high-order addresses reserved for future device densities d[15:0] input/ output data inputs/outputs: inputs data and commands during write cycles; outputs data during read cycles. data signals float when the device or its outputs are deselected. data are internally latched during writes. clk input flash clock: clk synchronizes the selected flash die to the memory bus frequency in synchronous-read mode. during synchronous read operations, the initial address is latched on the rising edge of adv#, or the rising/ falling edge of clk when adv# is low, whichever occurs first. clk is only used in synchronous-read mode. refe r to the flash discrete product datasheet for information on how to use this signal in asynchronous-read mode. adv# input flash address valid: low-true; during synchronous read operations, the initial address is latched on the rising edge of adv#, or the rising/ falling edge of clk when adv# is low, whichever occurs first. refer to the flash discrete product datasheet fo r information on how to use this signal in asynchronous-read mode. wait output flash wait: when asserted, wait indicates invalid data from the selected flash die on d[15:0]. wait is high-z whenever the flash die is deselected (ce# = v il ). wait is not gated by oe#. wait is only used in synchronous array-read mode. refer to the flash discrete product datasheet for information on how to use this signal in asynchronous-read mode. f[3:1]-ce# input flash chip enable: low-true; ce#-low selects the associat ed flash memory die. when asserted, flash internal control logic, input buffers, decoders , and sense amplifiers are active. when deasserted, the associated flash die is deselected; power is reduced to standby levels, data and wait outputs are placed in high-z. f1-ce# selects flash die #1; f2-ce# selects flash die #2 and is rfu on combinations with only one flash die. f3-ce# selects flash die #3 and is rfu on scsp combinations with only one or two flash die. s-cs1# s-cs2 input sram chip selects: when both sram chip selects are asserted, sram internal control logic, input buffers, decoders, and sense amplifiers are active. when either/both sram chip selects are deasserted (s-cs1# = v ih and/or s-cs2 = v il ), the sram is deselected and its power is reduced to standby levels. s-cs1# and s-cs2 are only available on scsp combinations with sram die. p[2:1]-cs# input psram chip selects: low-true; when asserted, psram internal control logic, input buffers, decoders, and sense amplifiers are active. when deasserted, the psram is deselected and its power is reduced to standby levels. p1-cs# selects psram die #1 and is available only on scsp combinations with psram die. this ball is rfu on scsp combinations without psram. p2-cs# selects psram die #2 and is available only on scsp combinations with two psram die. this ball is rfu on scsp combinations without psram or with a single psram.
intel? wireless flash memory (w18/w30 scsp) datasheet intel? wireless flash memory (w18/w30 scsp) 18-oct-2005 order number: 251407, revision: 010 15 f[2:1]-oe# input flash output enable: low-true; oe#-low enables the flas h output buffers. oe#-high disables the flash output buffers, and places the flash outputs in high-z. f1-oe# controls the outputs of flash die #1; f2-oe# controls the outputs of flash die #2 and #3, and is available only on scsp combinations with two or three flash die and is rfu on scsp combinations with only one flash die. r-oe# input ram output enable: low-true; r-oe#-low enables the ram output buffers. r-oe#-high disables the ram output buffers, and places the ram outputs in high-z. r-oe# is only available on scsp combinations with ram die. r-ub# r-lb# input ram upper/ lower byte enables: low-true; during ram reads, r-ub#-low enables the ram high-order bytes on d[15:8], and r-lb#-low enables the ram low-order bytes on d[7:0]. r-ub# and r-lb# are only available on scsp combinations with either sram die or psram die. f-we# input flash write enable: low-true; we# controls writes to th e selected flash die. address and data are latched on the rising edge of we#. r-we# input ram write enable: low-true; r-we# controls writes to the ram die. r-we# is only available on scsp combinations with ram die. f-wp# input flash write protect: low-true; wp# enables/disables the lock-down protection mechanism of the flash die. wp#-low enables the lock-down mechanism- locked down blocks cannot be unlocked with software commands. wp#-high disables the lock-down mechanism, allowing locked down blocks to be unlocked with software commands. f-rst# input flash reset: low-true; rst#-low initializes flash intern al circuitry and disabl es flash operations. rst#-high enables flash operation. exit from rese t places the flash in asynchronous read array mode. f-vpp f-vpen power flash program/ erase power: a valid f-v pp voltage on this ball enables flash program/erase operations. flash memory array contents cannot be altered when f-v pp (v pen ) < v pplk (v penlk ). erase/ program operations at invalid f-v pp (v pen ) voltages should not be attempted. refer to the flash discrete product datasheet for additional details. f-v pen (erase/program/block lock enables) is not available for w18/w30 products. p-mode input psram mode: low-true; p-mode is used to enter/exit low power mode. low power mode is not applicable to 38 f2020w0ztq1, 38f2020w0zbq1, 38f2030w0ytq1, 38f2030w0ybq1, 38f2030w0ztq2, 38f2030w0 zbq2, 38f1030w0ztq0, 38f1030w0zbq0, 38f1030w0ytqe, 38f1030w0ybqe. p-mode is only available on scsp combinations with psram die. f[2:1]-vcc power flash logic power: f1-vcc supplies power to the core logic of flash die #1; f2-vcc supplies power to the core logic of flash die #2 and #3. write operations are inhibited when f-v cc < v lko . device operations at invalid f-v cc voltages should not be attempted. f2-vcc is only available on scsp combinations with two or three flash die, and is rfu on scsp combinations with only one flash die. s-vcc power sram power supply: supplies power to the sram die. s-vcc is only available on scsp combinations with sram die. p-vcc power psram power supply: supplies power to the psram die. p-vcc is only available on scsp combinations with psram die. vccq power flash output-buffer power: supplies power for the i/o output buffers. vss power ground: connect to ground. do not float any vss connection. rfu ? reserved for future use: reserve for future device functionality/ enhancements. du ? do not use: do not connect to any other signal, or power supply; must be left floating. table 3. signal descriptions (sheet 2 of 2) symbol type name and function
intel? wireless flash memory (w18/w30 scsp) 18-oct-2005 intel? wireless flash memory (w18/w30 scsp) datasheet 16 order number: 251407, revision: 010 5.0 maximum ratings and operating conditions 5.1 absolute maximum ratings warning: stressing the device beyond the ?absolute maximum ratings? may cause permanent damage. these are stress ratings only. notice: this document contains information available at the time of its release. the specifications are subject to change without notice. verify with your local intel sales office that you have the latest datasheet before finalizing a design . table 4. absolute maximum ratings parameter min max unit notes temperature under bias expanded ?25 +85 c 7 storage temperature ?55 +125 c voltage on any signal (except f[2:1]-v cc , v ccq, f-v pp, s-v cc and p-v cc) 1.8 v i/o ?0.2 +2.45 v 1,2,3 3.0 v i/o ?0.2 +3.6 v 2,3 f[2:1]-v cc voltage ?0.5 +2.45 v 2,3 v ccq , s-v cc and p-v cc voltage 1.8 v i/o ?0.2 +2.45 v 1,2,3 3.0 v i/o ?0.2 +3.6 v 2,3 f-v pp voltage ?0.2 +14.0 v 2,3,4,5 i sh output short circuit current ? 100 ma 6 notes: 1. 90 nm is only avail with the 1.8 v i/o. 2. all specified voltages are relative to v ss . minimum dc voltage is ?0.2 v on input/output signals, ? 0.2 v on f[2:1]-vcc and f-vpp signals. for 90 nm devices, during transit ions, this level may overshoot to ?1.5 v for periods < 20 ns, during transitions, may overshoot to f-v cc + 1.5 v for periods < 20 ns. 3. all specified voltages are relative to v ss . minimum dc voltage is ?0.2 v on input/output signals, ? 0.2 v on f[2:1]-vcc and f-vpp signals. for 130 nm devices, during transit ions, this level may overshoot to ?2 v for periods < 20 ns, during transitions, may overshoot to f-v cc + 2 v for periods < 20 ns. 4. maximum dc voltage on f-vpp may over shoot to +14.0 v for periods < 20 ns. 5. f-v pp program voltage is normally v ppl . the maximum dc voltage on f-v pp may overshoot to +14 v for periods < 20 ns. f-v pp can be v pph for 1000 erase cycles on main blocks, 2500 cycles on parameter blocks. 6. output shorted for no more than one second. no more than one output shorted at a time. 7. devices available with -30 o c temperature specifications ar e: 38f2020w0ztq1, 38f2020w0zbq1, 38f2030w0ytq1, 38f2030w0ybq1, 38f2030w0ztq2, 38f2030w0zbq2, 38f1030w0ztq0, 38f1030w0zbq0, 38f1030w0ytqe, 38f1030w0ybqe,
intel? wireless flash memory (w18/w30 scsp) datasheet intel? wireless flash memory (w18/w30 scsp) 18-oct-2005 order number: 251407, revision: 010 17 5.2 operating conditions warning: operation beyond the ?operating conditions? is not recommended and extended exposure beyond the ?operating conditions? may affect device reliability. 5.3 capacitance table 5. operating conditions symbol parameter flash + flash flash + sram flash + psram unit notes min max min max min max t c operating temperature ?25 +85 ?25 +85 ?25 +85 c 2 f-v cc flash supply voltage 1.7 1.95 1.7 1.95 1.7 1.95 v v ccq s-v cc p-v cc flash i/o voltage psram and sram supply voltage 3.0 v i/o 2.2 3.3 2.2 3.3 2.7 3.1 v 1.8 v i/o 1.7 1.95 1.7 1.95 1.8 1.95 v v ppl flash program logic level 0.9 1.95 0.9 1.95 0.9 1.95 v v pph flash factory program voltag e 11.4 12.6 11.4 12.6 11.4 12.6 v 1 note: 1. f-v pp is normally v ppl . f-vpp can be connected to 11.4 v?12. 6 v for 1000 cycles on main blocks for extended temperatures and 2500 cycles on parameter blocks at extended temperature. 2. devices available with -30 o c temperature specifications ar e: 38f2020w0ztq1, 38f2020w0zbq1, 38f2030w0ytq1, 38f2030w0ybq1, 38f2030w0 ztq2, 38f2030w0zbq2, 38f1030w0ztq0, 38f1030w0zbq0, 38f1030w0ytqe, 38f1030w0ybqe,. notice: refer to the 1.8-volt intel ? wireless flash memory datasheet (order number 290701) and 1.8-volt intel ? wireless flash memory with 3 volt i/0 datasheet (order number 290702) for flash capacitance details. for scsp products with two flash die, flash capacitances for each of the flash die need to be considered accordingly. table 6. sram, psram capacitance symbol parameter typ unit condition c in input capacitance 10 pf v in = 0.0 v, t c = 25 c, f = 1 mhz c out output capacitance 10 pf v out = 0.0 v, t c = 25 c, f = 1 mhz
intel? wireless flash memory (w18/w30 scsp) 18-oct-2005 intel? wireless flash memory (w18/w30 scsp) datasheet 18 order number: 251407, revision: 010 6.0 electrical specifications 6.1 dc characteristics sram and psram dc characteristics are shown in table 7 and table 8 . refer to the intel ? wireless flash memory (w18) datasheet (order number 290701) and the intel ? wireless flash memory (w30) datasheet (order number 290702) for flash dc characteristics. table 7. sram dc characteristics parameter description test conditions 1.8 v sram 3.0 v sram unit min max min max s-v cc voltage range 1.7 1.95 2.2 3.3 v v dr v cc for data retention 1.0 ? 1.5 ? v i cc operating current at min cycle time i io = 0 ma 4m?25?45 ma 8m?35?50 16m ? 40 ? 55 i cc2 operating current at max cycle time (1 s) i io = 0 ma 4m?4?10 ma 8m?6?10 16m ? 10 ? 15 i sb standby current s-cs1# s-v cc -0.2v or s-cs2 v ss +0.2v address/data toggling at minimum cycle time 4m?12?15 a 8m?20?25 16m ? 30 ? 45 i dr current in data retention mode 1.8 v sram: s-v cc = 1.0 v 3.0 v sram: s-v cc = 1.5 v 4m?6?5 a 8m?10?12 16m ? 18 ? 15 v oh output high voltage i oh = -100 a s-v cc - 0.15 ? s-v cc - 0.1 ?v v ol output low voltage i ol = 100 a, v ccmin -0.1 0.2 -0.1 0.1 v v ih input high voltage s-v cc - 0.4 s-v cc + 0.2 s-v cc - 0.4 s-v cc + 0.2 v v il input low voltage -0.2 0.4 -0.2 0.6 v i oh output high current ? ? ? ? ma i ol output low current ? ? ? ? ma *i il input leakage current -0.2 < v in < s-v cc + 0.2 v -1 +1 -1 +1 a *i ldr input leakage current in data retention mode -0.2 < v in < s-v cc + 0.2 v s-v cc = v dr -1 +1 -1 +1 a * input leakage currents include hi-z output leakage for bi-directional buffers with tri-state outputs.
intel? wireless flash memory (w18/w30 scsp) datasheet intel? wireless flash memory (w18/w30 scsp) 18-oct-2005 order number: 251407, revision: 010 19 table 8. psram dc characteristics parameter description test conditions 1.8 v psram 3.0 v psram unit note min max min max v cc voltage range 1.8 1.95 2.7 3.1 v i cc operating current at min cycle time i io = 0 ma 8m ? ? ? 30 ma 2 16m ? 30 ? 35 16m ? 20 ? ? ma 3 32m ? 35 ? 45 ma 2 i cc2 operating current at max cycle time (1 s) i io = 0 ma 8m ? ? ? 5 ma 2 16m ? 5 ? 7 32m ? ? ? 7 i sb standby current p-cs# p-v cc - 0.2v. all inputs stable (either high or low) 8m ? ? ? 80 a2, 4 16m ? 100 ? 100 p-cs# p-v cc - 0.2v or p-mode p-v cc - 0.2v address/data toggling at minimum cycle time 16m ? ? ? 85 a2, 5 32m ? 100 ? 100 i sbd deep power- down p-mode 0.2 v 16m ? ? ? 10 a2, 4 32m ? 30 ? 10 v oh output high voltage i oh = -0.5 ma 0.8p - v cc ?2.4?v4 i oh = -0.1 ma 1.4 ? p-v cc - 0.3 ?v5 v ol output low voltage i ol = 1 ma, ? 0.2p - v cc ?0.4v4 i ol = 0.1 ma, v ccmin -0.1 0.2 -0.1 0.3 v 5 v ih input high voltage 0.8p - v cc p-v cc + 0.3 p-v cc - 0.3 p-v cc + 0.2 v4 p-v cc - 0.3 p-v cc + 0.2 p-v cc - 0.4 p-v cc + 0.2 v5 v il input low voltage ?0.3 0.2p - v cc -0.2 0.5 v 4 ?0.2 0.4 -0.2 0.6 v 5
intel? wireless flash memory (w18/w30 scsp) 18-oct-2005 intel? wireless flash memory (w18/w30 scsp) datasheet 20 order number: 251407, revision: 010 i il input leakage current -0.2 < v in < p-v cc + 0.2 v -1 +1 -1 +1 a1, 2 i ol output leakage current -0.2 < v in < p-v cc + 0.2 v p-v cc = v dr -1 +1 -1 +1 a1, 2 notes: 1. input leakage currents include hi-z output leakage for bi-directional buffers with tri-state outputs. 2. all currents are in rms unless noted otherwise. 3. applicable only to parts 38f1030w0yxqf & 38f2030w0yxqf 4. applicable to parts with p-mode pin ( 38f2030w0zxq1, 38f2040w0yxq 0, 28f2240wwyxq0). 5. applicable to no-p-mode (38f1030w0yxqe, 38f1030w0yxq2, 38f1030w0zxq0, 38f2030w0yxq1, 38f2030w0yxqe, 38f2030w0yxq2, 38f2030w 0yxqf, 38f2030w0zxq 2, 38f2040w0zxq0) table 8. psram dc characteristics
intel? wireless flash memory (w18/w30 scsp) datasheet intel? wireless flash memory (w18/w30 scsp) 18-oct-2005 order number: 251407, revision: 010 21 7.0 ac characteristics 7.1 flash ac characteristics refer to the intel ? wireless flash memory (w18) datasheet (order number 290701) and intel ? wireless flash memory (w30) datasheet (order number 290702) 7.2 sram ac characteristics table 9. sram ac characteristics ? read operations #symbol 1 parameter min max unit notes r1 t rc read cycle time 70 ? ns 1 r2 t aa address to output delay ? 70 ns 1 r3 t co1 s-cs1# to output delay ? 70 ns 1 r3 t co2 s-cs2 to output delay ? 70 ns 1 r4 t oe r-oe# to output delay ? 35 ns 1 r5 t ba r-ub#, r-lb# to output delay ? 70 ns 1 r6 t lz s-cs1# or s-cs2 to output in low-z 5 ? ns 1,3,4 r7 t olz r-oe# to output in low-z 0 ? ns 1,4 r8 t hz s-cs1# or s-cs2 to output in high-z 0 25 ns 1,2,3,4 r9 t ohz r-oe# to output in high-z 0 25 ns 1,2,4 r10 t oh output hold (from address, s-cs1#, s-cs2 or r-oe# change, whichever occurs first) 0?ns 1 r11 t blz r-ub#, r-lb# to output in low-z 0 ? ns 1,4 r12 t bhz r-ub#, r-lb# to output in high-z 0 25 ns 1,4 note: 1. see figure 5, ?ac waveform sram read operations? . 2. timings of t hz and t ohz are defined as the time at which the output s achieve the open circuit conditions and are not referenced to output voltage levels. 3. at any given temperature and voltage condition, t hz (max) is less than t lz (max) both for a given device and from device to device interconnection. 4. sampled but not 100% tested.
intel? wireless flash memory (w18/w30 scsp) 18-oct-2005 intel? wireless flash memory (w18/w30 scsp) datasheet 22 order number: 251407, revision: 010 figure 5. ac waveform sram read operations table 10. sram ac characteristics ? write operations # symbol 1 parameter min max unit notes w1 t wc write cycle time 70 ? ns 1 w2 t as address setup to r-we# (s-cs1#) and r-ub#/r-lb# low 0 ? ns 1,4 w3 t wp r-we# (s-cs1#) pulse width 55 ? ns 1,2,3 w4 t dw data to write time overlap 30 ? ns 1 w5 t aw address setup to r-we# (s-cs1#) high 60 ? ns 1 w6 t cw s-cs1# (r-we#) setup to r-we# (s-cs1#) high 60 ? ns 1 w7 t dh data hold from r-we# (s-cs1#) high 0 ? ns 1 w8 t wr write recovery 0 ? ns 1,5 w9 t bw r-ub#, r-lb# setup to r-we# (s-cs1#) high 60 ? ns 1 notes: 1. see figure 6, ?ac waveform sram write operations? . 2. a write occurs during the overlap (t wp ) of low s-cs1# and low r-we#. a write begins when s-cs1# goes low and r- we# goes low with asserting r-ub# and r-lb# for single byte operation or simultaneously asserting r-ub#r-lb# and r-lb# for double byte operation. a write ends at the earliest high transition of s-cs1# and r-we#. 3. t wp is measured from s-cs1# low to the end of a write. 4. t as is measured from the address valid to the beginning of a write. 5. t wr is measured from the end of write to the address change. t wr applied in case a write ends as s-cs1# or r-we# goes high. address stable valid data r12 r11 r5 r10 r4 r2 r9 r7 r6 r8 r3 r1 r1 standby addresses s-cs1# s-cs2 r-oe# r-we# dat a r-ub#, r-lb#
intel? wireless flash memory (w18/w30 scsp) datasheet intel? wireless flash memory (w18/w30 scsp) 18-oct-2005 order number: 251407, revision: 010 23 figure 6. ac waveform sram write operations address stable data in w9 w9 w2 w7 w4 w5 w3 w3 w8 w6 w1 w1 standby addresses s-cs1# s-cs2 r-oe# r-we# dat a r-ub#, r-lb#
intel? wireless flash memory (w18/w30 scsp) 18-oct-2005 intel? wireless flash memory (w18/w30 scsp) datasheet 24 order number: 251407, revision: 010 7.3 psram ac characteristics table 11. psram ac characteristics (85ns or 88ns initial access) ? read operations # symbol parameter 5 1.8 v 3.0 v unit notes min max min max r1 t rc read cycle time 88 4,000 85 4,000 ns r2 t aa address to output delay ? 88 ? 85 ns r3 t co p-cs# to output delay ? 88 ? 85 ns r4 t oe r-oe# to output delay ? 65 ? 40 ns r5 t ba r-ub#, r-lb# to output delay ? 88 ? 85 ns r6 t lz p-cs# to output in low-z 10 ? 10 ? ns 1,2 r7 t olz r-oe# to output in low-z 5 ? 0 ? ns 2 r8 t hz p-cs# to output in high-z ? 25 0 25 ns 1,2,3 r9 t ohz r-oe# to output in high-z ? 25 0 25 ns 2,3 r10 t oh output hold (from address, p-cs# or r- oe# change, whichever occurs first) 5?0?ns r11 t blz r-ub#, r-lb# to output in low-z 5 ? 0 ? ns 2 r12 t bhz r-ub#, r-lb# to output in high-z ? 25 0 25 ns 2 pr1 t pc page cycle time 30 ? 40 ? ns 4 pr2 t pa page access time ? 30 ? 35 ns 4 note: 1. at any given temperature and voltage condition, t hz (max) is less than t lz (max) both for a given device and from device to device interconnection. 2. sampled but not 100% tested. 3. timings of t hz and t ohz are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. 4. 4-word page read only available for 32-mbit psram. no page mode feature for 16-mbit psram. 5. applicable to parts with 85ns or 88ns initial acce ss time: (38f2030w0zxq1, 38f2040w0yxq0, 38f2040w0zxq0, 28f2240wwyxq0).
intel? wireless flash memory (w18/w30 scsp) datasheet intel? wireless flash memory (w18/w30 scsp) 18-oct-2005 order number: 251407, revision: 010 25 table 12. psram ac characteristics (70ns initial access)? read operations #symbol 1 parameter 7 1.8 v 3.0 v unit notes min max min max r1 t rc read cycle time 70 15000 70 15000 ns 70 8000 ? ? 2 r2 t aa address to output delay ? 70 ? 70 ns r3 t co p-cs# to output delay ? 70 ? 70 ns r4 t oe r-oe# to output delay ? 45 ? 45 ns r5 t ba r-ub#, r-lb# to output delay ? 70 ? 70 ns r6 t lz p-cs# to output in low-z 5 ? 5 ? ns 3 r7 t olz r-oe# to output in low-z 0 ? 0 ? ns r8 t hz p-cs# to output in high-z 0 25 0 25 ns 3, 4 r9 t ohz r-oe# to output in high-z 0 25 0 25 ns 4 r10 t oh output hold (from address, p-cs# or r- oe# change, whichever occurs first) 0?0?ns r11 t blz r-ub#, r-lb# to output in low-z 0 ? 0 ? ns r12 t bhz r-ub#, r-lb# to output in high-z 0 25 0 25 ns pr1 t pc page cycle time 25 ? 25 ? ns 5 pr2 t pa page access time ? 25 ? 25 ns 5 t cel ce# low-time restriction ? 8,000 ns 4 ns 6 note: 1. see figure 7, ?ac waveform of psram read operations? on page 27 and figure 8, ?ac waveform of psram 4-word page read operation? on page 27 2. spec?s only applicable to parts 38f1030w0yxqf & 38f2030w0yxqf 3. at any given temperature and voltage condition, t hz (max) is less than t lz (max) both for a given device and from device to device interconnection. 4. timings of t hz and t ohz are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. 5. 4-word page read only available for 16-mbit psram. no page mode feature for 8-mbit psram. parts 38f1030w0yxqf & 38f2030w0yxqf do not support pa ge mode, so this spec will not apply to them 6. ce# must go high and be maintained high for a minimum of 10ns at least once every 8,000ns 7. applicable to 70ns initial access p-sram?s (38f1030w0yxqe, 38f1030w0yxq2, 38f1030w0zxq0, 38f2030w0yxq1, 38f2030w0yxqe, 38f2030w0yxq2, 38f2030w0yxqf, 38f2030w0zxq2)
intel? wireless flash memory (w18/w30 scsp) 18-oct-2005 intel? wireless flash memory (w18/w30 scsp) datasheet 26 order number: 251407, revision: 010 table 13. psram ac characteristics?write operations #symbol 1 parameter 7 1.8 v 3.0 v unit notes min max min max w1 t wc write cycle time 70 8000 70 ? ns w2 t as address setup to r-we# (p-cs#) and r-ub#, r-lb# going low 0? 0 ?ns4 w3 t wp r-we#(p-cs#) pulse width 55 ? 55 ? ns 2,3 w4 t dw data to write time overlap 35 ? 35 ? ns w5 t aw address setup to r-we# (p-cs#) going high 60 ? 60 ? ns w6 t cw p-cs# (r-we#) setup to r-we# (p-cs#) going high 60 ? 60 ? ns w7 t dh data hold from r-we# (p-cs#) high 0? 0 ?ns w8 t wr write recovery 0 ? 0 ? ns 5 w9 t bw r-ub#, r-lb# setup to r-we# (p-cs#) going high 60 ? 60 ? ns t cel p-ce# low-time restriction ? 8,000 ? ? ns 7,8 w10 t wph write high pulse width 10 ? ? ? ns 8 notes: 1. see figure 9, ?ac waveform psram write operation? . 2. a write occurs during the overlap (t wp ) of low p-cs# and low r-we#. a write begins when p-cs# goes low and r-we# goes low with asserting r-ub# or r-lb# for single byte operation or simultaneously asserting r-ub# and r-lb# for double byte operation. a write ends at the earliest transition when p-cs# goes high and r-we# goes high. 3. t wp is measured from p-cs# going low to end of a write. 4. t as is measured from the address valid to the beginning of a write. 5. t wr is measured from the end of a write to the address change. t wr applied in case a write ends as p-cs# or r-we# going high. 6. w3 is 70 ns for continuous write operations over 50 times. 7. p-ce# must go high and be maintained high fo r a minimum of 10ns at least once every 8,000ns 8. spec?s only applicable to parts 38f1030w0yxqf & 38f2030w0yxqf 9. applicable to 38f2020w0ztq1, 38f2020w0zbq1, 38f2030w0ytq1, 38f2030w0ybq1, 38f2030w0ztq2, 38f2030w0zbq2, 38f1030w0ztq0, 38f1030w 0zbq0, 38f1030w0ytqe, 38f1030w0ybqe.
intel? wireless flash memory (w18/w30 scsp) datasheet intel? wireless flash memory (w18/w30 scsp) 18-oct-2005 order number: 251407, revision: 010 27 note: available only for 32-mbit psram and line items with 16-mbit psram (70 ns) 38f2030w0ytq1, 38f2030w0ybq1, 38f2030w0ztq2, 38f2030w0zbq2, 38f1030w0ztq0, 38f1030w0zbq0, 38f1030w0ytqe, 38f1030w0ybqe. not applicable to 8-mbit psram. figure 7. ac waveform of psram read operations figure 8. ac waveform of psram 4-word page read operation valid data r10 r6 r11 r7 r9 r4 r12 r5 r8 r3 r1 r2 r1 addresses p-cs# r-ub#, r-lb# r-oe# dat a valid addres s valid addres s valid addres s valid addres s valid addres s valid data valid data valid data valid data pr2 r6 r7 r9 r4 r8 r3 pr1 pr1 r1 r2 r1 a [max:2] a[1:0] p-cs# r-oe# dat a
intel? wireless flash memory (w18/w30 scsp) 18-oct-2005 intel? wireless flash memory (w18/w30 scsp) datasheet 28 order number: 251407, revision: 010 figure 9. ac waveform psram write operation data in w7 w4 w8 w5 w3 w3 w9 w6 w1 w2 w1 addresses p-cs# r-ub#, r-lb# r-we# dat a
intel? wireless flash memory (w18/w30 scsp) datasheet intel? wireless flash memory (w18/w30 scsp) 18-oct-2005 order number: 251407, revision: 010 29 7.4 device ac test conditions figure 10. transient input/output reference waveform note: ac test inputs are driven to v ccq , p-v cc for logic ?1? and 0.0 v for logic ?0?. input/output timing begins/ ends at v ccq /2, p-v cc /2. input rise and fall time (10% to 90%) < 5 ns. worse case speed occurs at v cc = v ccmin . figure 11. transient equivalent testing load circuit notes: 1. test configuration component value for worst case specification conditions. 2. c l includes jig capacitance. test points v ccq /2, p-v cc /2 v ccq /2, p-v cc /2 input output 0 v v ccq , p-v cc i/o output z o = 50 ohms c l = 30 pf 50 ohms p-v cc /2 = v ccq /2
intel? wireless flash memory (w18/w30 scsp) 18-oct-2005 intel? wireless flash memory (w18/w30 scsp) datasheet 30 order number: 251407, revision: 010 8.0 flash power consumption refer to the intel ? wireless flash memory (w18) datasheet (order number 290701) and intel ? wireless flash memory (w30) datasheet (order number 290702) for information regarding flash read modes and operations.
intel? wireless flash memory (w18/w30 scsp) datasheet intel? wireless flash memory (w18/w30 scsp) 18-oct-2005 order number: 251407, revision: 010 31 9.0 device operation 9.1 bus operations bus operations for the w18/w30 scsp family involve the following chip enable and output enable signals, respectively: ? f1-ce# for flash die#1 and f2-ce# for flash die#2 ? f1-oe# for flash die#1 and f2-oe# for flash die#2 all other control signals are shared between the two flash die. table 14 to table 16 explain the bus operations of products across this scsp family. refer to the w18/w30 discrete datasheets (order numbers 290701 and 290702) for single flash die scsp bus operations. table 14. flash-only bus operations device mode f-rst# f1-ce# f1-oe# f-we# adv# f-vpp wait f2-ce# f2-oe# d[15:0] notes flash die#1 sync array read h l l h l x active h x flash d out 2, 3, 4 all async / sync non-array read hllhx xasserted h x flash d out 1, 3, 4, 5 write h l h l x v ppl or v pph asserted h x flash d in 3, 4, 6 output disable h l h h x x active x x flash high-z 4 standby h h x x x x high-z x x flash high-z 4 reset lxxxx x high-z x x flash high-z 4
intel? wireless flash memory (w18/w30 scsp) 18-oct-2005 intel? wireless flash memory (w18/w30 scsp) datasheet 32 order number: 251407, revision: 010 flash die#2 sync array read h h x h l x active l l flash d out 2, 3, 4 all async / sync non-array read hhxhx xasserted l l flash d out 1, 3, 4, 5 write h h x l x v ppl or v pph asserted l h flash d in 3, 4, 6 output disable h x x h x x active l h flash high-z 4 standby hxxxx x high-z h x flash high-z 4 reset lxxxx x high-z x x flash high-z 4 notes: 1. for asynchronous read operation, both die may be simultaneously selected, but may not simultaneously drive the memory bus. see section 9.2, ?flash command definitions? on page 34 for details regarding flash selection overlap. 2. wait is only valid during synchronous flash reads. wait is driven if f-ce# is asserted. refer to the w18 or w30 datasheet (order number 290701 and 29702) for further information regarding wait signal. 3. for either flash die, f[2:1]-oe# and f-we# should neve r be asserted simultaneously. if done so on a particular flash die, f[2:1]-oe# will override f-we#. 4. l means v il while h means v ih . x can be v il or v ih for inputs, v ppl , v pph or v pplk for f-vpp. 5. flash cfi query and status register accesses use d[7:0] only, all other reads use d[15:0]. 6. refer to w18/w30 datasheet for valid d in during flash writes. table 15. flash + sram bus operations device mode f-rst# f[2:1]-ce# f[2:1]-oe# f-we# adv# f-vpp wait s-cs1# s-cs2 r-oe# r-we# r-ub#, r-lb# d[15:0] notes flash die(#1 or #2) sync array read hllhl x active sram must be in high-z flash d out 1, 2, 3, 5 all async/ sync non-array read h l l h x x asserted flash d out 1, 2, 3, 5, 6 write h l h l l v ppl or v pph asserted flash d in 3, 7 output disable hlhhx x active any sram mode allowed flash high-z 5 standby hhxxx x high-z flash high-z 5 reset lxxxx x high-z flash high-z 5 device mode f-rst# f1-ce# f1-oe# f-we# adv# f-vpp wait f2-ce# f2-oe# d[15:0] notes
intel? wireless flash memory (w18/w30 scsp) datasheet intel? wireless flash memory (w18/w30 scsp) 18-oct-2005 order number: 251407, revision: 010 33 sram read flash must be in high-z lhlhl sram d out 1, 4, 8, 2 write l h x l l sram d in 4, 5, 8, 2 output disable any flash mode allowed l hhh x sram high-z 5, 2 standby hx xx x sram high-z 5, 8, 2 xl data retention same as sram standby sram high-z 9, 2 notes: 1. for asynchronous read operation, all die may be simu ltaneously selected, but may not simultaneously drive the memory bus. 2. wait is only valid during synchronous flash reads. wait is driven if f-ce# is asserted. 3. for flash die, f[2:1]-oe# and f-we# should never be asserted simultaneously. if done so, f[2:1]-oe# will override f-we#. 4. for sram, r-oe# and r-we# should never be asserted simultaneously. 5. x can be v il or v ih for inputs, v ppl , v pph or v pplk for f-vpp. 6. flash cfi query and status register accesses use d[7:0] only, all other reads use d[15:0]. 7. refer to w18 and w30 datasheet for valid d in during flash writes. 8. the sram is enabled and/or disabled with the logical function: s-cs1# or s-cs2. 9. the sram can be placed into data retention mode by lowering s-vcc to the v dr limit when in standby mode. table 16. flash + psram bus operations device mode f-rst# f[2:1]-ce# f[2:1]-oe# f-we# adv# f-vpp wait p-cs# p-mode r-oe# r-we# r-ub#, r-lb# d[15:0] notes flash die(#1 or #2) sync array read hllhl xactive psram must be in high-z flash d out 1, 2, 3, 4, 6 all async/ sync non-array read h l l h x x asserted flash d out 1, 2, 3, 4, 6, 7 write h l h l x v ppl or v pph asserted flash d in 3, 4, 6, 8 output disable hlhhx xactive any psram mode allowed flash high-z 6 standby h h x x x x high-z flash high-z 6 reset lxxxx xhigh-z flash high-z 6 table 15. flash + sram bus operations device mode f-rst# f[2:1]-ce# f[2:1]-oe# f-we# adv# f-vpp wait s-cs1# s-cs2 r-oe# r-we# r-ub#, r-lb# d[15:0] notes
intel? wireless flash memory (w18/w30 scsp) 18-oct-2005 intel? wireless flash memory (w18/w30 scsp) datasheet 34 order number: 251407, revision: 010 9.2 flash command definitions refer to the discrete datasheets, intel ? wireless flash memory (w18) datasheet (order number 290701) and intel ? wireless flash memory (w30) datasheet (order number 290702) for information regarding flash command definitions. psram read flash#1 and #2 must be in high-z lhlhl psram d out 1, 5, 2 write l h h l l psram d in 5, 2 output disable any flash mode allowed l hhh x psram high-z 6, 2 standby h h x x x psram high-z 6, 2 deep power- down hlxxx psram high-z 6, 9, 2 notes: 1. for asynchronous read operation, all die may be simultaneously selected, but may not simultaneously drive the memory bus. for synchronous burst-mode reads, only two die (one flash and the psram) may be simultaneously selected. 2. wait is only valid during synchronous flash re ads. wait is driven if f-ce# is asserted. 3. f1-ce# for flash die#1, f2-ce# for flash die#2. f1-oe# is for flash die#1, f2-oe# for flash die#2. 4. for either flash die, f[2:1]-oe# and f-we# should never be a sserted simultaneously. if done so on a particular flash die, f[2 :1]- oe# will override f-we#. 5. for psram, r-oe# and r-we# should never be asserted simultaneously. 6. x can be v il or v ih for inputs, v ppl ,v pph or v pplk for f-vpp. 7. flash cfi query and status register accesses use d[7:0] only, all other reads use d[15:0]. 8. refer to w30/w18 datasheet for valid d in during flash writes. 9. deep power-down is not applicable to 38f2020w0 ztq1, 38f2020w0zbq1, 38f2030w0ytq1, 38f2030w0ybq1, 38f2030w0ztq2, 38f2030w0zbq2, 38f1030w0ztq0, 38f1030w0zbq0, 38f1030w0ytqe, 38f1030w0ybqe. table 16. flash + psram bus operations device mode f-rst# f[2:1]-ce# f[2:1]-oe# f-we# adv# f-vpp wait p-cs# p-mode r-oe# r-we# r-ub#, r-lb# d[15:0] notes
intel? wireless flash memory (w18/w30 scsp) datasheet intel? wireless flash memory (w18/w30 scsp) 18-oct-2005 order number: 251407, revision: 010 35 10.0 flash read operations refer to the intel ? wireless flash memory (w18) datasheet (order number 290701) and intel ? wireless flash memory (w30) datasheet (order number 290702) for information regarding flash read modes and operations.
intel? wireless flash memory (w18/w30 scsp) 18-oct-2005 intel? wireless flash memory (w18/w30 scsp) datasheet 36 order number: 251407, revision: 010 11.0 flash program operations refer to the intel ? wireless flash memory (w18) datasheet (order number 290701) and intel ? wireless flash memory (w30) datasheet (order number 290702) for information regarding flash read modes and operations.
intel? wireless flash memory (w18/w30 scsp) datasheet intel? wireless flash memory (w18/w30 scsp) 18-oct-2005 order number: 251407, revision: 010 37 12.0 flash erase operations refer to the intel ? wireless flash memory (w18) datasheet (order number 290701) and intel ? wireless flash memory (w30) datasheet (order number 290702) for information regarding flash read modes and operations.
intel? wireless flash memory (w18/w30 scsp) 18-oct-2005 intel? wireless flash memory (w18/w30 scsp) datasheet 38 order number: 251407, revision: 010 13.0 flash security modes refer to the intel ? wireless flash memory (w18) datasheet (order number 290701) and intel ? wireless flash memory (w30) datasheet (order number 290702) for information regarding flash read modes and operations.
intel? wireless flash memory (w18/w30 scsp) datasheet intel? wireless flash memory (w18/w30 scsp) 18-oct-2005 order number: 251407, revision: 010 39 14.0 flash read conf iguration register refer to the intel ? wireless flash memory (w18) datasheet (order number 290701) and intel ? wireless flash memory (w30) datasheet (order number 290702) for information regarding flash read modes and operations.
intel? wireless flash memory (w18/w30 scsp) 18-oct-2005 intel? wireless flash memory (w18/w30 scsp) datasheet 40 order number: 251407, revision: 010 15.0 sram operations 15.1 power-up sequence and initialization the sram functionality and reliability are independent of the power-up sequence and power-up slew rate of the core s-v cc . any power-up sequence and power-up slew rate is possible under use conditions. sram reliability is also independent of the power-down sequence and power-down slew rate of the core s-v cc . 15.2 data retention mode table 17. sram data retention operation symbol parameter min max unit notes t sdr data retention set-up time 0 ? ns t rdr data retention recovery time t rc ?ns 1 note: 1. t rc is defined in table 7.2, ?sram ac characteristics? on page 21 . figure 12. sram data retention operation waveform?s-cs1# controlled s-v cc s-v ccmin s-v ihmin v dr v ss t sdr data retention mode t rdr s-cs1#
intel? wireless flash memory (w18/w30 scsp) datasheet intel? wireless flash memory (w18/w30 scsp) 18-oct-2005 order number: 251407, revision: 010 41 figure 13. sram data retention operation waveform?s-cs2 controlled s-v cc s -v ccmin v dr v ilmax v ss s-cs2 t sdr data retention mode t rdr
intel? wireless flash memory (w18/w30 scsp) 18-oct-2005 intel? wireless flash memory (w18/w30 scsp) datasheet 42 order number: 251407, revision: 010 16.0 psram operations 16.1 power-up sequence and initialization the psram functionality and reliability are independent of the power-up sequence and slew rate of the core p-v cc . any power-up sequence and slew rate is possible under use conditions. psram reliability are also independent of the power-down sequence and slew rate of the core p-v cc . the following power-up sequence and register setting should be used before starting normal operation. the psram power-up sequence is represented in figure 14 . following power application, make p-mode high after fixing p-mode to a low level for a period of t i1 . make p-cs# high before making p-mode high. p-cs# and p-mode are fixed to a high level for period of t i3 . 16.1.1 16mbit psram power-up sequence (non-page mode) for the non-page mode psram (part?s rd38f1030w0yqf, pf38f1030w0yqf, rd38f2030w0yqf, pf38f2030w0yqf) the psram functionality and reliability must be independent of the power-up sequence and power-up slew rate of the core vcc and the i/o vcc figure 14. timing waveform for power-up sequence table 18. power-up sequence specifications parameter description min max unit notes t i1 power application with p-mode held low 50 ? s 1,2,3 t i2 p-cs# high to p-mode high 10 ? ns t i3 p-mode high to p-cs# low 500 ? s notes: 1. toggle p-mode to low when starting the power-up sequence. 2. t i1 is specified from when the power supply voltage reaches v ccmin . 3. does not apply to 38f2020w0ztq1, 38f2020w0zbq1, 38f2030w0ytq1, 38f2030w0ybq1, 38f2030w0ztq2, and 38f2030w0zbq2, 38f1030w0ztq0, 38f1030w0zbq0, 38f1030w0ytqe, 38f1030w0ybqe line items. valid psram operations for these line items can begin 200 s after p- vcc has reached p-vcc min. register setting ti3 ti1 ti2 power up p-vcc p-cs# p-mode
intel? wireless flash memory (w18/w30 scsp) datasheet intel? wireless flash memory (w18/w30 scsp) 18-oct-2005 order number: 251407, revision: 010 43 (vccq.) any power-up sequence and power-up slew rate is possible under use conditions. psram reliability must also be independent of the power-down sequence and power-down slew rate of the core vcc and the i/o vcc (vccq.) once power supply voltages have reached the minimum spec value of 1.7v (or higher), ce# must be maintained high for minimum 200us prior to commencing valid psram operation. 16.2 standby mode/ deep power-down mode caution: all line items that do not have the p-mode pine will not have the deep power-down feature (38f1030w0yxqe, 38f1030w0yxq2, 38f1030w0zxq0, 38f2030w0yxq1, 38f2030w0yxqe, 38f2030w0yxq2, 38f2030w0yxqf, 38f2030w0zxq2, 38f2040w0zxq0). data is lost during deep power-down mode as shown in the table below. wake-up from deep power-down mode involves the same initialization sequence as discussed in section 16.1, ?power- up sequence and initialization? on page 42 . 16.3 psram special read and write constraints caution: this section will not apply to line items that do not have the p-mode pine will not have the deep power-down feature (38f1030w0yxqe, 38f1030w0yxq2, 38f1030w0zxq0, 38f2030w0yxq1, 38f2030w0yxqe, 38f2030w0yxq2, 38f2030w0yxqf, 38f2030w0zxq2, 38f2040w0zxq0). mode memory cell data delay time to go active standby valid 0 ns deep power-down invalid start-up sequence figure 15. timing waveform for entering deep power-down mode table 19. psram special read constraints description min max unit notes cannot have sub t rc address toggle for more than 4 s in active mode. need either a read operation or p-cs# high for t rc in that time frame n/a n/a ? p-cs# high level pulse width 10 ? ns 1 deep power down mode deep power down mode suspend mode 1 us p-mode p-cs# device mode
intel? wireless flash memory (w18/w30 scsp) 18-oct-2005 intel? wireless flash memory (w18/w30 scsp) datasheet 44 order number: 251407, revision: 010 r-ub#/r-lb# high level pulse width 10 ? ns 1 r-oe# high level pulse width in active mode (p-cs# low) 10 10,000 ns p-cs# low to r-oe# low ? 10,000 ns address skew time (unstable address with p-cs# low) ? 10 ns 2 notes: 1. toggling of these control signals is not nec essary during address controlled read operations. 2. address skew time (t skew ) indicates the following three types of time depending on the condition. a. when switching p-cs# from high to low, t skew is the time from the p-cs# low input point until the next address is determined. b. when switching p-cs# from low to high, t skew is the time from the address change start point to the p-cs# high input point. c. when p-cs# is fixed to low, t skew is the time from the address start point until the next address is determined. since specs are defined for t skew only when p-cs# is active, t skew is not subject to limitations when p-cs# is switched from high to low following address determination, or when the address is changed after p-cs# is switched from low to high. table 20. psram special write constraints description min max unit notes need either r-we# high or p-cs# high for at least t wc time, for every 4us window during write operations. n/a n/a ? r-oe# high to r-we# low in active mode (p-cs# low) 0 10,000 ns r-we# high to r-oe# low in active mode (p-cs# low) 10 10,000 ns address skew time (unstable address with p-cs# low) ? 10 ns 1 note: 1. address skew time (t skew ) indicates the following three types of time depending on the condition. a. when switching p-cs# from high to low, t skew is the time from the p-cs# low input point until the next address is determined. b. when switching p-cs# from low to high, t skew is the time from the address change start point to the p-cs# high input point. c. when p-cs# is fixed to low, t skew is the time from the address start point until the next address is determined. since specs are defined for t skew only when p-cs# is active, t skew is not subject to limitations when p-cs# is switched from high to low following address determination, or when the address is changed after p-cs# is switched from low to high. table 19. psram special read constraints
intel? wireless flash memory (w18/w30 scsp) datasheet intel? wireless flash memory (w18/w30 scsp) 18-oct-2005 order number: 251407, revision: 010 45 appendix a write state machine refer to the intel ? wireless flash memory (w18) datasheet (order number 290701) and intel ? wireless flash memory (w30) datasheet (order number 290702) for the wsm details.
intel? wireless flash memory (w18/w30 scsp) 18-oct-2005 intel? wireless flash memory (w18/w30 scsp) datasheet 46 order number: 251407, revision: 010 appendix b common flash interface refer to the intel ? wireless flash memory (w18) datasheet (order number 290701) and intel ? wireless flash memory (w30) datasheet (order number 290702) for the cfi details.
intel? wireless flash memory (w18/w30 scsp) datasheet intel? wireless flash memory (w18/w30 scsp) 18-oct-2005 order number: 251407, revision: 010 47 appendix c flash flowcharts refer to the intel ? wireless flash memory (w18) datasheet (order number 290701) and intel ? wireless flash memory (w30) datasheet (order number 290702) for the flash flowchart details.
intel? wireless flash memory (w18/w30 scsp) 18-oct-2005 intel? wireless flash memory (w18/w30 scsp) datasheet 48 order number: 251407, revision: 010 appendix d additional information : order number document 290701 intel ? wireless flash memory (w18) datasheet 290702 intel ? wireless flash memory with 3 volt i/o (w30) datasheet 251216 64-mbit 1.8 volt intel ? wireless flash memory scsp family application note notes: 1. please call the intel literature center at (800) 548-4725 to request intel documentation. international customers should contact their local intel or distribution sales office. 2. for the most current information on intel ? flash memory products, software and tools, visit our website at http://developer.intel.com/design/flash.
intel? wireless flash memory (w18/w30 scsp) datasheet intel? wireless flash memory (w18/w30 scsp) 18-oct-2005 order number: 251407, revision: 010 49 appendix e ordering information figure 16 shows the decoder for products in this scsp family with both flash and ram. figure 17 shows the decoder for products in this scsp family with flash die only (no ram). table 23, ?32wq and 64wq w18/w30 scsp ordering information (flash + psram)? on page 52 lists available product combinations. figure 16. decoder for flash + ram scsp family devices f 2 0 w 0 z b q 8 d 3 r package pinout indicator product line designator flash density voltage product family rd = scsp pf = pb-free scsp 38f = flash & ram stack device 2 = 64-mbit 1 = 32-mbit 0 = no die w = intel? wireless flash memory 0 = no die y = 1.8 volt i/o z = 3 volt i/o q= quad+ ballout 3 0 ram density 4 = 32-mbit 3 = 16-mbit 2 = 8-mbit 1 = 4-mbit 0 = no die 0 parameter location b = bottom parameter t = top parameter d = dual parameter device details 0-9, a-d = 1 st generation, 130 nm e-r = 2 nd generation, 90 nm (note: 90 nm is only 1.8 v i/o) s-z = 3 rd generation, tbd flash #1 flash #2 ram #2 ram #1 flash #1 family flash #2 family
intel? wireless flash memory (w18/w30 scsp) 18-oct-2005 intel? wireless flash memory (w18/w30 scsp) datasheet 50 order number: 251407, revision: 010 notes: figure 17. decoder for flash-only scsp family devices table 21. 32wq and 64wq w18/w30 scsp ordering information (flash only) flash component package product number (1,2,3,4,5) size (mm) type ballout 32 w30 8 x 10 x 1.2 lead-free quad + pf48f1000w0ztq0 pf48f1000w0zbq0 64 w30 8 x 10 x 1.2 lead-free quad + pf48f2000w0ztq0 pf48f2000w0zbq0 64 w18 + 32 w18 8 x 10 x 1.2 leaded quad + rd48f2100w0ydqe 64 w18 + 64w18 8 x 10 x 1.2 leaded quad + rd48f2200w0ydq0 f 2 2 w 0 z d q 8 d 4 r package pinout indicator product line designator flash density voltage product family rd = scsp pf = pb-free scsp 48f = flash-only stack device 2 = 64-mbit 1 = 32-mbit 0 = no die w = intel? wireless flash memory 0 = no die y = 1.8 volt i/o z = 3 volt i/o q = quad+ ballout 0 0 0 parameter location d = dual parameter flash # 1 flash # 2 flash 1/2 family flash # 4 flash # 3 flash 3/4 family device details 0-9, a-d = 1 st generation, 130 nm e-r = 2 nd generation, 90 nm (note: 90 nm is only 1.8 v i/o) s-z = 3 rd generation, tbd b = bottom parameter t = top parameter
intel? wireless flash memory (w18/w30 scsp) datasheet intel? wireless flash memory (w18/w30 scsp) 18-oct-2005 order number: 251407, revision: 010 51 1. w18 = intel ? wireless flash memory (w18) with 1.8 v i/o; w30 = intel ? wireless flash memory (w30) with 3.0 v i/o. 2. b = bottom parameter, where flash die #1, f1-ce# = bottom parameter and flash die #2, f2-ce# = top parameter. 3. t = top parameter where flash die #1, f1-ce# = top parameter and flash die #2, f2-ce# = bottom parameter. 4. d = dual parameter where flash die #1, f1-ce# = bottom parameter and flash die #2, f2-ce# = top parameter. 5. parts ending with ?qe? are 90 nm flash devices. notes: 1. w18 = intel ? wireless flash memory (w18) with 1.8 v i/o; w30 = intel ? wireless flash memory (w30) with 3.0 v i/o. 2. b = bottom parameter, where flash die #1, f1-ce# = bottom parameter and flash die #2, f2-ce# = top parameter. 3. t = top parameter where flash die #1, f1-ce# = top parameter and flash die #2, f2-ce# = bottom parameter. 4. d = dual parameter where flash die #1, f1-ce# = bottom parameter and flash die #2, f2-ce# = top parameter. table 22. 32wq and 64wq w18/w30 scsp ordering information (flash + sram) flash component ram package product number (1,2,3,4) size in mbit and family size in mbit and type size (mm) type ballout 64 w18 4 sram 8 x 10 x 1.2 leaded quad+ rd38f2010w0ytq0 rd38f2010w0ybq0 8 sram 8 x 10 x 1.2 leaded quad+ rd38f2020w0ytq0 rd38f2020w0ybq0 16 sram 8 x 10 x 1.2 leaded quad+ rd38f2030w0ytq0 rd38f2030w0ybq0 64 w30 8 sram 8 x 10 x 1.2 leaded quad+ rd38f2020w0ztq0 rd38f2020w0zbq0 16 sram 8 x 10 x 1.2 leaded quad+ rd38f2030w0ztq0 rd38f2030w0zbq0 64 w18 + 64 w18 16 sram 8 x 10 x 1.4 leaded quad+ rd38f2230wwydq0 64 w30 + 64 w30 16 sram 8 x 10 x 1.4 leaded quad+ rd38f2230wwzdq0
intel? wireless flash memory (w18/w30 scsp) 18-oct-2005 intel? wireless flash memory (w18/w30 scsp) datasheet 52 order number: 251407, revision: 010 table 23. 32wq and 64wq w18/w30 scsp ordering information (flash + psram) (sheet 1 of 2) flash component ram package product number (1,2,3,4,5) psram used size in mbit and family size in mbit and type size (mm) ballout type 32 w18 16 psram 8 x 10 x 1.2 quad+ lead-free pf38f1030w0ytqe pf38f1030w0ybqe 70 ns, no pmode pin 32 w18 16 psram 8 x 10 x 1.2 quad+ leaded rd38f1030w0ytq2 rd38f1030w0ybq2 70 ns, no pmode pin & non-page mode support lead-free pf38f1030w0ytq2 pf38f1030w0ybq2 32 w30 16 psram 8 x 10 x 1.2 quad+ leaded rd38f1030w0ztq0 rd38f1030w0zbq0 70 ns, no pmode pin lead-free pf38f1030w0ztq0 pf38f1030w0zbq0 64 w18 16 psram 8 x 10 x 1.2 quad+ leaded rd38f2030w0ytq1 rd38f2030w0ybq1 70 ns, no pmode pin lead-free pf38f2030w0ytq1 pf38f2030w0ybq1 leaded rd38f2030w0ytqe rd38f2030w0ybqe lead-free pf38f2030w0ytqe pf38f2030w0ybqe 64 w18 16 psram 8 x 10 x 1.2 quad+ leaded rd38f2030w0ytq2 rd38f2030w0ybq2 70 ns, no pmode pin & non-page mode support lead-free pf38f2030w0ytq2 pf38f2030w0ybq2 leaded rd38f2030w0ytqf rd38f2030w0ybqf lead-free pf38f2030w0ytqf pf38f2030w0ybqf 64 w30 16 psram 8 x 10 x 1.2 quad+ leaded rd38f2030w0ztq1 rd38f2030w0zbq1 85 ns, with pmode pin leaded rd38f2030w0ztq2 rd38f2030w0zbq2 70 ns, no pmode pin lead-free pf38f2030w0ztq2 pf38f2030w0zbq2 64 w18 32 psram 8 x 10 x 1.2 quad+ leaded rd38f2040w0ytq0 rd38f2040w0ybq0 88 ns, with pmode pin lead-free pf38f2040w0ytq0 pf38f2040w0ybq0
intel? wireless flash memory (w18/w30 scsp) datasheet intel? wireless flash memory (w18/w30 scsp) 18-oct-2005 order number: 251407, revision: 010 53 notes: 1. w18 = intel ? wireless flash memory (w18) with 1.8 v i/o; w30 = intel ? wireless flash memory (w30) with 3.0 v i/o. 2. b = bottom parameter, where flash die #1, f1-ce# = bottom parameter and flash die #2, f2-ce# = top parameter. 3. t = top parameter where flash die #1, f1-ce# = top parameter and flash die #2, f2-ce# = bottom parameter. 4. d = dual parameter where flash die #1, f1-ce# = bottom parameter and flash die #2, f2-ce# = top parameter. 5. parts ending with ?qe? are 90 nm flash devices. 6. rd38f2240wwydq0 = engineering samples; RD38F2240WWYDQ1 = production 64 w30 32 psram 8 x 10 x 1.2 quad+ leaded rd38f2040w0ztq0 rd38f2040w0zbq0 85 ns, no pmode pin 64 w18 + 64 w18 32 psram 8 x 10 x 1.4 quad+ leaded rd38f2240wwydq0 (6) RD38F2240WWYDQ1 88 ns, with pmode pin 64 w30 + 64 w30 32 psram 8 x 10 x 1.4 quad+ leaded rd38f2240wwzdq0 rd38f2240wwzdq1 85 ns, no pmode pin table 23. 32wq and 64wq w18/w30 scsp ordering information (flash + psram) (sheet 2 of 2) flash component ram package product number (1,2,3,4,5) psram used size in mbit and family size in mbit and type size (mm) ballout type
intel? wireless flash memory (w18/w30 scsp) 18-oct-2005 intel? wireless flash memory (w18/w30 scsp) datasheet 54 order number: 251407, revision: 010

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